1. Technical Field
The present invention relates to doped wells, and more particularly, to doped biasing wells used to reduce threshold voltage variation in semiconductor integrated circuits.
2. Related Art
Fabricating a semiconductor device such that it has a target threshold voltage as designed is difficult. One of the methods for achieving the target threshold voltage as designed is to form a highly-doped well under the channel region of the semiconductor device and use well (voltage) bias as a means of adjusting the threshold voltage to the target. However, the highly-doped biasing well results in leakage current between itself and the source/drain regions of the semiconductor device as well as increased junction capacitance, particularly at the edge of the junctions beneath the channel.
Therefore, there is a need for a novel structure in the semiconductor device to eliminate or reduce such leakage current and such junction capacitance. There is also a need for a method for fabricating such a novel structure.